dimarts, 16 de febrer del 2021

RISC-V Intructions

I don't like very much the distributed style of RISC-V instruction description of the official RISC-V ISA https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf 

So I try to do my own, maybe someone else find it useful

Registers

Register ABI Name Description
x0zeroHardwired zero (READ ONLY)
x1raReturn Address
x2spStack Pointer
x3gpGlobal Pointer
x4tpThread Pointer
x5t0Temporary/alternate link register
x6-x7t1-t2Temporaries
x8s0/fpSaved register/frame pointer
x9s1Saved register
x10-x11a0-a1Function arguments/return values
x12-x17a2-a7Function arguments
x18-x27s2-s11Saved registers
x28-x31t3-t6Temporaries

Types of Instructions

assuming the Instruction is a 32 bit value IR , we describe bit vectors in Verilog style IR[6:0] means the lower 7 bits of variable IR. 


opcode=IR[6:0]  (7 bits)
funct3=IR[14:12] (3 bits)
funct7=IR[31:25] (7 bits)
rs1=IR[19:15] (5 bits)
rs2=IR[24:20] (5 bits)
rd=IR[11:7]  (5 bits)
imm12=IR[31:20]
imm20=IR[31:12]
shamt=IR[24:20]
imm_btype={IR[31],IR[7],IR[30:25],IR[11:8],0}
imm_stype={IR[31:25],IR[11:7]}
imm_btype={IR[]}
imm_jtype={IR[31],IR[19:12],IR[20],IR[30:21], 0}

Type Description Meaningful Fields
R    Registeropcode, funct3, funct7, rs1, rs2, rd
IImmediateopcode, funct3, rs1, rd, imm12
S        Storeopcode, funct3, rs1, rs2, imm_stype
BBranch offsetopcode, funct3, rs1, rs2, imm_btype
U?opcode, rd, imm20
JJumpopcode, rd, imm_jtype

Instructions

ADDI (opcode=0x13, funct3=0x00, I-Type)

Add immediate

[rd] = [rs1] + signExtend(imm12) 

BNE (opcode=0x63, funct3=0x01)

Branch Not Equal

if ([rs1] != [rs2])  pc = pc + signExtend(imm_btype)

ECALL (opcode=0x73, )

Executive System Call

JAL (opcode=0x6F, J-Type)

Jump and link. x0 is allowed as rd register, but it is obviously not written.

[rd] = [pc]+4

[pc] = [pc] + signExtend(imm_jtype)

JALR (opcode=0x67, I-Type)

Jump and link register. x0 is allowed as rd register, but it is obviously not written.

[rd] = [pc]+4

[pc] = ([rs1] + signExtend(imm12) ) & ~0x1

LBU (opcode=0x03, funct3=0x04, I-Type)

Load Byte Unsigned

add = [rs1]+signExtend(imm12)

add32 = add & ~0x3

addby = add & 0x3

[rd] = zeroExtend(([add]>>addby) & 0xFF)

LW (opcode=0x03, funct3=0x02, I-Type)

Load Word

add = [rs1]+signExtend(imm12)

[rd] = [add]

SW (opcode, S-Type)

Store Word

add = [rs1]+signExtend(imm_stype)

SLLI (opcode=0x13, funct3=0x01, I-Type)

Shift Left Immediate

[rd] = [rs1] << shamt


Fast Table

Opcode Funct3 Funct7InstructionISA
0x030x0LBRV32I
0x030x1LHRV32I
0x030x2LWRV32I
0x030x4LBURV32I
0x030x5LHURV32I
0x130x0ADDIRV32I
0x130x10x0SLLIRV32I
0x130x50x0SRLIRV32I
0x130x2SLTIRV32I
0x130x3SLTIURV32I
0x130x4XORIRV32I
0x130x6ORIRV32I
0x130x7ANDIRV32I
0x17AUIPCRV32I
0x230x0SBRV32I
0x230x1SHRV32I
0x230x2SWRV32I
0x230x3SDRV64I


0x330x00x00ADDRV32I
0x330x00x01MULRV32M
0x330x00x20SUBRV32I
0x330x10x00SLLRV32M
0x330x10x01MULHRV32M
0x330x20x01MULHSURV32M
0x330x30x00SLTURV32I
0x330x30x01MULHURV32M
0x330x40x00XORRV32I
0x330x40x01DIVRV32M
0x330x50x01DIVURV32M
0x330x60x00ORRV32I
0x330x60x01REMRV32M
0x330x70x00ANDRV32M
0x330x70x01REMURV32M

0x37LUIRV32I
0x630x0BEQRV32I
0x630x1BNERV32I
0x630x4BLTRV32I
0x630x5BGERV32I
0x630x6BLTURV32I
0x630x7BGEURV32I
0x670x0JALR
0x6FJAL
0x73SYSTEM    


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